Jacqueline Genow


Recent Posts

Enyx launches the nxAccess HLS Trading Platform

[fa icon="calendar'] May 23, 2019 / by Jacqueline Genow posted in Press-Release

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An innovative approach to making FPGA technology more accessible

Enyx, a leader in ultra-low latency FPGA-based technology and solutions, is proud to announce the addition of an HLS development framework for nxAccess -- Enyx's ultra low-latency Market Access solution.

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Enyx IP Core technology featured by Xilinx at 2019 Mobile World Congress

[fa icon="calendar'] April 01, 2019 / by Jacqueline Genow posted in Events

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Enyx, a leader in ultra-low latency FPGA-based technology and solutions, is proud to announce that its 25G TCP/IP Core technology was featured by Xilinx, Inc. at the 2019 Mobile World Congress in Barcelona last month. Xilinx utilized the Enyx TCP offload engine to power its demonstration on application layer security offload for high efficiency in telecom data centers.

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Enyx provides 10G TCP Acceleration Function Unit and development framework for Intel® Programmable Acceleration Card with Intel Arria® 10 GX

[fa icon="calendar'] November 12, 2018 / by Jacqueline Genow posted in Press-Release, Events

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Stop by booth #240 to learn more about Enyx and our participation in Intel's partner program

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Terasic chooses Enyx to offer ultra-low latency development framework for their latest FPGA platform

[fa icon="calendar'] September 26, 2018 / by Jacqueline Genow posted in Press-Release, Events

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Combining ultra-low latency FPGA IP cores and market access technology with next-gen FPGA platforms for high performance, trading solutions available for the APAC region. 

New York, Hong Kong, Taipei – September 26, 2018 – Terasic, the premier developer of Intel FPGA platforms today announced a partnership with Enyx, the leading independent provider of FPGA-enabled, ultra-low latency trading technologies, offering integrated Enyx FPGA IPs for an ultra-low latency, customized development framework on Terasic’s DE5a-Net DDR4 accelerator.

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